Più nero di un cielo senza stelleGuida Editori, 2004 - 396 páginas |
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Página v
... gate determines whether it is cost efficient to encode the states of a hardwired control automaton. If this ratio is smaller than 2, encoding is no option for rea- sonably sized automata. • In a non-pipelined DLX design, hardwired ...
... gate determines whether it is cost efficient to encode the states of a hardwired control automaton. If this ratio is smaller than 2, encoding is no option for rea- sonably sized automata. • In a non-pipelined DLX design, hardwired ...
Página 2
... gates. In two steps we then augment the model to include first registers and then also RAM and tristate drivers. It turns out, that the rules which govern the enabling and disabling drivers can be captured with a very simple and ...
... gates. In two steps we then augment the model to include first registers and then also RAM and tristate drivers. It turns out, that the rules which govern the enabling and disabling drivers can be captured with a very simple and ...
Página 3
... gate, binary coding is not a realistic option for the implementation of reasonable sized automata (20 to 50 states). If on the other hand the relative cost of flipflops is high, i.e., a flipflop is at least 8 times more expensive than ...
... gate, binary coding is not a realistic option for the implementation of reasonable sized automata (20 to 50 states). If on the other hand the relative cost of flipflops is high, i.e., a flipflop is at least 8 times more expensive than ...
Página 9
... gates, flipflop, RAM, with the standard meaning. Their cost is measured in gate equivalents [g] and their propagation delays in gate delays [d]. These values are normalized to the cost (delay) of an 1-bit inverter. The parameters can be ...
... gates, flipflop, RAM, with the standard meaning. Their cost is measured in gate equivalents [g] and their propagation delays in gate delays [d]. These values are normalized to the cost (delay) of an 1-bit inverter. The parameters can be ...
Página 10
... gate delays. Thus, the whole delay of this RAM is caused by its select and decode logic. In our model, ROMs have the same delay as RAMs but they are usually cheaper by afactor ROMfac. The reference guide of the Motorola system [NB93] ...
... gate delays. Thus, the whole delay of this RAM is caused by its select and decode logic. In our model, ROMs have the same delay as RAMs but they are usually cheaper by afactor ROMfac. The reference guide of the Motorola system [NB93] ...
Contenido
1 | |
10 | |
21 | |
43 | |
59 | |
Design of thè DLX Machine | 77 |
TradeOff Analyses | 123 |
Interrupt | 141 |
Microprogrammed Control | 179 |
Further Applications of thè Architecture Model | 199 |
A Register Transfer Language | 201 |
Bibliography | 263 |
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Términos y frases comunes
accumulated delay active adder address architecture arithmetic unit benchmark binary bits carry look-ahead chapter circuit combinatorial components computation computes conditional sum control automaton control signals control unit cost and delay critical path current cycle time data paths decode decoder Diego directly DLX design DLX machine encoder environment extern int fanout fetch Figure first following formulae function gates generates guardò hardware hardwired control impact indicates inputs instruction set interrupt handling interrupt service routine inverter istante lists Load main memory mamma MARK Mealy implementation memory status time microcoded control microinstruction modified monomials Moore implementation Motorola Motorola technology multiplexer n-bit number occhi opcode order output overflow Paola papà path powerup printf program program counter provides purpose registers quality parameter R-type ragazzo read requires return rispose run time same section shift shifter stava Table thè three unary coding used Valerio value write zero tester