Più nero di un cielo senza stelleGuida Editori, 2004 - 396 páginas |
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Página 6
... indicates the frequency of instruction 7 in the workload. 2.2. Quality. Metrics. We evaluate the designs based on a benchmark Be that models the workload W and is usually written in the high level programming language Pr. The compiler Co ...
... indicates the frequency of instruction 7 in the workload. 2.2. Quality. Metrics. We evaluate the designs based on a benchmark Be that models the workload W and is usually written in the high level programming language Pr. The compiler Co ...
Página 9
... indicated as Motorola technology is based on Motorola's H4C CMOS sea-of-gate design series [NB93]. The second technology is based on the VENUS design System [HNS86, Sie88]. Table 2.1 lists cost and delay of the basic components under ...
... indicated as Motorola technology is based on Motorola's H4C CMOS sea-of-gate design series [NB93]. The second technology is based on the VENUS design System [HNS86, Sie88]. Table 2.1 lists cost and delay of the basic components under ...
Página 14
... indicates which operation should be performed. With an inactive write signal (w=0), data are read from the RAM. The RAM behaves like the combination r(0) of registers and combinatorial circuit Sr in figure 2.5, where the delay DST of ...
... indicates which operation should be performed. With an inactive write signal (w=0), data are read from the RAM. The RAM behaves like the combination r(0) of registers and combinatorial circuit Sr in figure 2.5, where the delay DST of ...
Página 17
... indicates that main memory can not complete the access in the current cycle of the hardware. The flag pagefault signals that the requested data lies on a memory block (page) which is not available during the current cycle. While the ...
... indicates that main memory can not complete the access in the current cycle of the hardware. The flag pagefault signals that the requested data lies on a memory block (page) which is not available during the current cycle. While the ...
Página 18
... indicates powerup. So far, our model has no device that generates external signals. This is easily fixed: an external input is simply a signal that can be used like the output of a flipflop and that may change its value at the beginning ...
... indicates powerup. So far, our model has no device that generates external signals. This is easily fixed: an external input is simply a signal that can be used like the output of a flipflop and that may change its value at the beginning ...
Contenido
1 | |
10 | |
21 | |
43 | |
59 | |
Design of thè DLX Machine | 77 |
TradeOff Analyses | 123 |
Interrupt | 141 |
Microprogrammed Control | 179 |
Further Applications of thè Architecture Model | 199 |
A Register Transfer Language | 201 |
Bibliography | 263 |
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Términos y frases comunes
accumulated delay active adder address architecture arithmetic unit benchmark binary bits carry look-ahead chapter circuit combinatorial components computation computes conditional sum control automaton control signals control unit cost and delay critical path current cycle time data paths decode decoder Diego directly DLX design DLX machine encoder environment extern int fanout fetch Figure first following formulae function gates generates guardò hardware hardwired control impact indicates inputs instruction set interrupt handling interrupt service routine inverter istante lists Load main memory mamma MARK Mealy implementation memory status time microcoded control microinstruction modified monomials Moore implementation Motorola Motorola technology multiplexer n-bit number occhi opcode order output overflow Paola papà path powerup printf program program counter provides purpose registers quality parameter R-type ragazzo read requires return rispose run time same section shift shifter stava Table thè three unary coding used Valerio value write zero tester